TSMC Reaffirms Stance on High-NA EUV Lithography at European Technology Symposium
At the European Technology Symposium in Amsterdam, TSMC reaffirmed its longstanding position regarding the use of next-generation High-NA EUV lithography tools. The semiconductor giant announced it will not adopt these advanced systems for its forthcoming A16 (1.6nm-class) and A14 (1.4nm-class) process technologies. Kevin Zhang, TSMC’s Deputy Co-COO and Senior Vice President of Business Development, stated, “We will use High-NA only when it provides meaningful benefits. Our A14 enhancements are substantial without it.”
TSMC’s A14 process leverages second-generation nanosheet gate-all-around transistors and a new cell architecture, achieving up to 15% higher performance or 25-30% lower power consumption compared to earlier nodes. The A14 node also boasts a 20% increase in transistor density. This marked advancement is part of what TSMC calls the "full node advantage," achieved without the need for High-NA EUV tools, ensuring predictable yields and performance.
Notably, the A16 process, a variation of N2P with a Super Power Rail design, will not require High-NA either, distinguishing TSMC’s approach from competitors like Intel, which plans to implement these tools in their upcoming manufacturing technologies starting in 2027-2028. Zhang emphasized TSMC’s ongoing innovation, stating, "Our technology team continues to find ways to extend the life of current EUV while maximizing scaling benefits."
While TSMC’s A14 will enter mass production by 2028, prospects for the subsequent A14 iteration in 2029 also seem to follow suit, indicating a future without reliance on High-NA EUV until at least 2030 or beyond. TSMC’s strategy highlights its focus on innovation and efficiency in chip manufacturing.
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